1. Field of the Invention
The present invention is generally in the field of semiconductor devices. More specifically, the present invention is in the field of semiconductor memory devices.
2. Background Art
Electronic devices utilizing non-volatile semiconductor memory are decreasing in size while requiring an increased amount of non-volatile data storage capacity, creating a need for non-volatile memory cells that can be manufactured inexpensively on a smaller scale. Non-volatile memory cells can be formed using a “double-poly” structure, in which a control gate and a floating gate are each formed in a separate polycrystalline silicon (also referred to as polysilicon) layer. However, double-poly processes are expensive due to the additional manufacturing steps required to form the multiple polysilicon layers.
In one conventional non-volatile memory cell, the gate of a MOS transistor, which acts as a floating gate, is coupled to a MOS capacitor, which acts as a control gate. Although these memory cells do not utilize the costly double-poly process, they tend to consume a very large amount of the semiconductor surface area since the MOS capacitors must be implemented in the semiconductor substrate and laid out laterally to the MOS transistors. Non-volatile memory cells with MOS capacitors also require observing minimum spacing requirements that add to the consumption of the semiconductor area. For example, if a PMOS is utilized as the MOS capacitor and the MOS transistor is an NMOS, a relatively large minimum space between the MOS capacitor NWELL and the N+ diffusions of the NMOS transistor is required to provide adequate electrical isolation, which also causes the memory cell to be larger. In addition, MOS capacitors can suffer from charge leakage through the gate dielectric, as well as junction leakage from the NWELL to the silicon substrate, resulting in a memory cell with decreased data retention reliability.
There is thus a need in the art for a scaleable non-volatile memory cell that occupies a small area of the semiconductor die, can be manufactured at a reduced cost and has improved data retention reliability.